1. Field of the Invention
The present invention relates to a power semiconductor device, and particularly to an insulated gate semiconductor device favorably used as a power switching element.
2. Description of the Related Art
In recent years, power supply devices used in the power electronics field are strongly required to be more compact with higher performance. In accordance with this demand, power semiconductor devices have been improved to operate with lower loss and fewer noises, as well as higher breakdown voltage and larger electric current. Under the circumstances, an IEGT (Injection Enhanced Gate Transistor) obtained by improving an IGBT (Insulated Gate Bipolar Transistor) is attracting attention as a device, which can reduce the turn-off loss, as well as reducing the on-state voltage (for example, Jpn. Pat. Appln. KOKAI Publication No. 5-24356; Jpn. J. Appl. Phys. Vol. 36 (1997) pp. 3433-3437, ISSCC 2000 Digest Paper TA7.2; and M. Kitagawa et al., xe2x80x9cA 4500V Injection Enhanced Insulated Gate Bipolar Transistor (IEGT) in a Mode Similar to a Thyristorxe2x80x9d, IEDM ""93, pp. 679-682, 1993).
FIG. 25 is a sectional view showing a conventional IEGT having a trench structure. As shown in FIG. 25, on one side of an n-base layer 101, an n-buffer layer 102 is disposed, and a p-collector layer 103 is further disposed thereon. On the other side of the n-base layer 101, a plurality of trenches 104 are formed at intervals in the n-base layer 101, such that main cells MR and dummy cells DR are alternately partitioned.
In each of the main cells MR, a p-base layer 107 is disposed on the n-base layer 101. N-emitter layers 108 are formed in the surface of the p-base layer 107. In each of the dummy cells DR, a p-buffer layer 109 is disposed on the n-base layer 101. Dividing a common p-layer by the trenches 104 forms the p-base layers 107 and p-buffer layers 109.
A collector electrode 111 is disposed on the p-collector layer 103. An emitter electrode 112 is disposed on the p-base layer 107 and n-emitter layers 108. A gate electrode 106 is buried in each of the trenches 104, while it is wrapped in a gate insulating film 105. As a consequence, an n-channel MOSFET is formed in the main cell MR, such that it selectively connects the n-emitter layer 108 to the n-base layer 101, using the p-base layer 107 as a channel region, to inject electrons.
In the sectional view shown in FIG. 25, the surface of the p-buffer layer 109 in each of the dummy cells DR is covered with an insulating film 110. However, in order to fix the potential of the p-buffer layer 109, a part of the emitter electrode 112 is also disposed on the p-buffer layer 109 at a position not shown in FIG. 25. The density of the part of the emitter electrode 112 disposed on the p-buffer layer 109 is small, so that the resistance between the p-buffer layer 109 and emitter electrode 112 is equivalently large.
In this IEGT, each of the main cells MR forms a narrow current passage connecting the n-base layer 101 to the emitter electrode. 112. In the on-state of the IEGT, this arrangement provides an increase in resistance against the flow of holes from the n-base layer 101 into the emitter electrode 112 through the p-base layer 107 in the main cell MR, thereby restricting the holes being exhausted into the emitter electrode 112. As a consequence, the injection efficiency of electrons from the n-emitter layers 108 into the n-base layer 101 improves, thereby promoting conductivity modulation of the n-base layer 101, resulting in a low on-state voltage.
A CSTBT (Carrier Stored Trench-Gate Bipolar Transistor) has also been proposed as a power semiconductor device, which can reduce the on-resistance as in the IEGT (for example, H. Takahashi et al., xe2x80x9cCarrier Stored Trench-Gate Bipolar Transistor (CSTBT)xe2x80x94A Novel Power Device for High Voltage Applicationxe2x80x9d ISPSD ""96, pp. 349-352, 1996). FIG. 26 is a sectional view showing a conventional CSTBT.
As shown in FIG. 26, on one side of an n-base layer 131, a p-collector layer 133 is disposed. On the other side of the n-base layer 131, an n-barrier layer 132 having an impurity concentration higher than that of the n-base layer 131 is disposed. A p-base layer 137 is disposed on the n-barrier layer 132. N-emitter layers 138 are formed in the surface of the p-base layer 137. A plurality of trenches 134 are formed at intervals such that they extend from the substrate surface into the n-base layer 131.
A collector electrode 141 is disposed on the p-collector layer 133. An emitter electrode 142 is disposed on the p-base layer 137 and n-emitter layers 138. A gate electrode 136 is buried in each of the trenches 134, while it is wrapped in a gate insulating film 135. As a consequence, an n-channel MOSFET is formed such that it selectively connects the n-emitter layer 138 to the n-base layer 131, using the p-base layer 137 as a channel region, to inject electrons.
In this CSTBT, the n-barrier layer 132 having a high impurity concentration provides a large resistance against flow of holes. In the on-state of the CSTBT, this arrangement provides an increase in resistance against the flow of holes from the n-base layer 131 into the emitter electrode 142 through the p-base layer 137, thereby restricting the holes being exhausted into the emitter electrode 142. As a consequence, the injection efficiency of electrons from the n-emitter layers 138 into the n-base layer 131 improves, thereby promoting conductivity modulation of the n-base layer 131, resulting in a low on-state voltage.
The conventional IEGT and CSTB, used as power semiconductor devices, have the advantage of providing a low on-state voltage. However, these conventional power semiconductor devices have a problem causing a large noise in switching, and especially being turned on, as described above. In addition, since the resistance against holes being exhausted is high, a problem arises in that a period of time (storage period) for a depletion layer to extend up from the start of voltage rising is prolonged when the devices are turned off. This increases the turn-off loss, as well as the turn-off time.
According to a first aspect of the present invention, there is provided a power semiconductor device comprising:
a first base layer of a first conductivity type;
a collector layer of a second conductivity type disposed on the first base layer;
a plurality of trenches disposed in the first base layer at intervals to partition a main cell and a dummy cell, at a position remote from the collector layer;
a second base layer of the second conductivity type disposed on the first base layer in the main cell;
an emitter layer of the first conductivity type disposed on the second base layer;
a buffer layer of the second conductivity type disposed on the first base layer in the dummy cell;
a gate electrode disposed in a trench of the plurality of trenches, adjacent to the main cell, to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;
a collector electrode disposed on the collector layer;
an emitter electrode disposed on the second base layer and the emitter layer; and
a buffer resistor inserted between the buffer layer and the emitter electrode,
wherein the main cell forms a current passage narrow enough to provide, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer, and
the buffer resistor has a resistance value smaller than that with which gate-emitter voltage is increased by gate negative capacity, in a period of time for an applied voltage between gate and emitter to charge capacity between gate and collector, in process of turn-on of the device.
According to a second aspect of the present invention, there is provided a power semiconductor device comprising:
a first base layer of a first conductivity type;
a collector layer of a second conductivity type disposed on the first base layer;
a plurality of trenches disposed in the first base layer at intervals to partition a main cell and a dummy cell, at a position remote from the collector layer;
a second base layer of the second conductivity type disposed on the first base layer in the main cell;
an emitter layer of the first conductivity type disposed on the second base layer;
a buffer layer of the second conductivity type disposed on the first base layer in the dummy cell;
a gate electrode disposed in a trench of the of trenches, adjacent to the main cell, to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;
a collector electrode disposed on the collector layer;
an emitter electrode disposed on the second base layer and the emitter layer; and
a buffer resistor inserted between the buffer layer and the emitter electrode and having an infinitely large resistance value,
wherein the main cell forms a current passage narrow enough to provide, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer, and
the dummy cell is provided with an inhibiting structure configured to reduce a quantity of carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer, in a period of time for an applied voltage between gate and emitter to charge capacity between gate and emitter, in process of turn-on of the device, as compared to a case where the buffer layer and the second base layer are formed with the same impurity concentration and depth.
According to a third aspect of the present invention, there is provided a power semiconductor device comprising:
a first base layer of a first conductivity type;
a collector layer of a second conductivity type disposed on the first base layer;
a plurality of trenches disposed in the first base layer at intervals to partition a main cell and a dummy cell, at a position remote from the collector layer;
a second base layer of the second conductivity type disposed on the first base layer in the main cell;
an emitter layer of the first conductivity type disposed on the second base layer;
a buffer layer of the second conductivity type disposed on the first base layer in the dummy cell;
a gate electrode disposed in a trench of the plurality of trenches, adjacent to the main cell, to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;
a collector electrode disposed on the collector layer;
an emitter electrode disposed on the second base layer and the emitter layer; and
a buffer resistor inserted between the buffer layer and the emitter electrode and having an infinitely large resistance value,
wherein the main cell forms a current passage narrow enough to provide, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer, and
a switching element configured to selectively connect the buffer layer to the second base layer is formed at a position beyond an end of the gate electrode in a channel width direction, and carriers of the second conductivity type are exhausted from the buffer layer to the second base layer through the switching element, in a period of time for an applied voltage between gate and emitter to charge capacity between gate and emitter, in process of turn-on of the device.
According to a fourth aspect of the present invention, there is provided a power semiconductor device comprising:
a first base layer of a first conductivity type;
a collector layer of a second conductivity type disposed on the first base layer;
a trench disposed in the first base layer at a position remote from the collector layer;
a second base layer of the second conductivity type disposed on the first base layer and in contact with the trench;
an emitter layer of the first conductivity type disposed on the second base layer;
a gate electrode disposed in the trench to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;
a collector electrode disposed on the collector layer;
an emitter electrode disposed on the second base layer and the emitter layer;
a barrier layer of the first conductivity type disposed between the first base layer and the second base layer, and having an impurity concentration higher than that of the first base layer, the barrier layer providing, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer;
a diverter layer of the second conductivity type disposed on the first base layer, to exhaust carriers of the second conductivity type from the first base layer; and
a rectifying element including a portion of the first conductivity type electrically connected to the emitter electrode, and a portion of the second conductivity type electrically connected to the diverter layer, the rectifying element becoming conductive by a change in potential of the diverter layer, thereby exhausting carriers of the second conductivity type from the diverter layer into the emitter electrode, in process of turn-off of the device.
According to a fifth aspect of the present invention, there is provided a power semiconductor device comprising:
a first base layer of a first conductivity type;
a collector layer of a second conductivity type disposed on the first base layer;
a trench disposed in the first base layer at a position remote from the collector layer;
a second base layer of the second conductivity type disposed on the first base layer and in contact with the trench;
an emitter layer of the first conductivity type disposed on the second base layer;
a gate electrode disposed in the trench to face, through a gate insulating film, a portion of the second base layer sandwiched between the first base layer and the emitter layer;
a collector electrode disposed on the collector layer;
an emitter electrode disposed on the second base layer and the emitter layer;
a barrier layer of the first conductivity type disposed between the first base layer and the second base layer, and having an impurity concentration higher than that of the first base layer, the barrier layer providing, in an on-state of the device, an increase in resistance against flow of carriers of the second conductivity type from the first base layer into the emitter electrode through the second base layer, thereby improving injection efficiency of carriers of the first conductivity type from the emitter layer into the first base layer;
a diverter layer of the second conductivity type disposed on the first base layer, to exhaust carriers of the second conductivity type from the first base layer; and
an MOSFET with a second conductivity type channel configured to be driven by a driving electrode electrically connected to the gate electrode to selectively connect the diverter layer to the emitter electrode, the MOSFET with a second conductivity type channel becoming conductive by a change in potential of the driving electrode, thereby exhausting carriers of the second conductivity type from the diverter layer into the emitter electrode, in process of turn-off of the device.